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    • 专利摘要:
    The invention describes a method of forming spacers of a gate (150) of a field effect transistor (100), the gate (150) including flanks and a vertex and being located above a layer (146) of a semiconductor material, the method comprising a step (410) of forming a dielectric layer (152) overlying the gate of the transistor, the method comprising: - after the step of forming the dielectric layer (152), at least one step of modifying (430) said dielectric layer (152) by placing the dielectric layer (152) in contact with a plasma creating a light ion bombardment; at least one step of removing (440) the modified dielectric layer (158), characterized in that the step of removing (440) the modified dielectric layer (158) comprises: a dry etching (441) carried out by in the presence of a gaseous mixture, preferably a gaseous mixture, comprising at least a first component based on hydrofluoric acid (HF), the hydrofluoric acid transforming the modified dielectric layer into non-volatile residues (158); (442) nonvolatile residues by wet cleaning performed only after dry etching (441) or thermal sublimation annealing performed after or during dry etching (441).
    公开号:FR3041471A1
    申请号:FR1558845
    申请日:2015-09-18
    公开日:2017-03-24
    发明作者:Olivier Pollet；Nicolas Posseme
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    TECHNICAL FIELD OF THE INVENTION
    The present invention generally relates to field effect transistors (FETs) used by the microelectronics industry and more particularly to the realization of gate spacers of metal-oxide-semiconductor (MOSFET) type transistors mainly used for the production of all kinds of integrated circuits.
    STATE OF THE ART
    The incessant race to reduce dimensions that characterizes the entire microelectronics industry has been achieved only with the contribution of key innovations throughout decades of development since the first integrated circuits were produced industrially in the sixties. A very important innovation that dates back to the seventies, and is still used, is to make the MOSFET transistors using a technique in which the source and drain electrodes are self aligned with those of the grid and do not therefore do not require a photoengraving operation for their definition. Combined with the use of polycrystalline silicon grids, it is the grids themselves, made first, which serve as a mask during the doping of the source and drain regions of the transistors.
    Figure 1a is a sectional view of an example of this type of transistor 100 in progress. It contains the source and drain areas 110, generally designated source / drain zones, since they are very generally perfectly symmetrical and can play both roles depending on the electric polarizations that are applied to the transistor. The grid conventionally consists of a stack of layers 120, a large part of which is always composed of polycrystalline silicon 123. The formation of the source and drain zones is typically done by ion implantation 105 of dopants in the zones 110, the grid 120 serving mask as mentioned above, thus preventing the doping of the area of the MOSFET transistor in which, depending on the voltages applied to the gate, will be able to develop the channel 130 of conduction between source and drain.
    The basic technique, very briefly described above, well known to those skilled in the art as well as many variants, has been constantly improved in order to improve the electrical performance of the transistors while allowing to accommodate the reductions of successive size of the transistors required by an ever increasing integration of a larger number of components in an integrated circuit.
    A widely used technique currently consists in manufacturing the integrated circuits starting from elaborate substrates 140 of silicon-on-insulator type, designated by their acronym SOI, of the English "Silicon on insulator". The SOI developed substrate is characterized by the presence of a thin superficial layer of monocrystalline silicon 146 resting on a continuous layer of silicon oxide 144, called buried oxide or BOX, acronym for "buried oxide layer". The strength and the mechanical rigidity of the assembly are ensured by the layer 142 which constitutes the body of the SOI substrate, often described as "bulk" to indicate that the starting substrate is very generally made of solid silicon. This structure offers many advantages for the realization of MOSFET transistors. In particular, it allows a drastic reduction of parasitic capacitances due to the presence of the insulating continuous layer 144. With regard to the invention, it will be retained only that the surface layer of monocrystalline silicon 146 can be precisely controlled in thickness and in doping . In particular, it is advantageous for the performance of the transistors that the channel 130 can be completely deserted carriers, that is to say "fully depleted" (FD), English term which is generally used to designate this state. This is achieved by producing the transistors from SOI substrates whose surface layer 146 is very thin, which is not without disadvantage otherwise as will be seen in the description of the invention. This type of transistor is thus designated by the acronym FDSOI.
    An improvement in the basic self-alignment technique that has been universally adopted is the formation of spacers 150 on the flanks of the grid. The spacers 150, typically made of silicon nitride (SiN), will allow in particular the implementation of a technique called "Source and Drain elevated". In order to maintain low electrical resistance to access the source and drain electrodes, despite the size reduction of the transistors, it was indeed necessary to increase their section. This is obtained by selective epitaxy of the source / drain zones 110. During this operation, the initial layer of monocrystalline silicon 14 will be grown locally 112. It is then necessary to protect the grid areas to prevent the growth from also being made from polycrystalline silicon 123 of the grid. It is, among other things, the role of spacers to ensure this function. They also perform a role of preserving the gate during siliciding of the contacts (not shown) which is then performed for the same purpose in order to reduce the series resistance of access to the electrodes of the transistor.
    The formation of the spacers 150 has become a crucial step in the formation of transistors that now reach dimensions that are commonly measured in nanometers (nm = 10'9 meters) and which are generally of decananometric size. The spacers are made without involving any photoengraving operation. They are self-aligned on the gate 120 from the deposition of a uniform layer of silicon nitride 152 (SiN) which then undergoes a very strongly anisotropic etching. This etching of the SiN preferentially attacks the horizontal surfaces, that is to say all the surfaces that are parallel to the plane of the SOI substrate. It leaves in place, imperfectly, only the vertical portions of the layer 152, those substantially perpendicular to the plane of the substrate, in order to obtain in practice the patterns 150 whose ideal shape would obviously be rectangular.
    With the known solutions, the size reduction of the transistors makes it very difficult to obtain spacers that fully play their role of isolation and do not induce defects in the production of transistors from SOI substrates. Indeed, in the context of the present invention, and as will be detailed later, it has been found that several types of defect such as those mentioned below appear during the etching of the spacers using one or the other. other known methods of anisotropic etching.
    Figures 1b, 1c and 1d each illustrate a type of defect observed.
    In particular, a type of etching is used which is said to be "dry" and which is implemented using a process which is most often referred to by its acronym RIE, of the English "reactive-ion eching", c 'ie reactive ion etching'. It is an etching process in which a plasma is formed in a confined space that reacts physically and chemically with the surface of the wafer to be etched. In the case of the etching of a silicon nitride layer, which is, as we have seen, the preferred material for producing the spacers, the reactive gas is typically methyl fluoride (CH 3 F) which is reacted. with the material to be etched by also introducing oxygen (02). An etching plasma based on fluorine chemistry is thus formed and often designated by its constituents: CH3F / 02 / He. In this plasma, the fluorine compound serves to etch the silicon nitride whereas the oxygen makes it possible to limit the polymerization of the methyl fluoride and also serves to oxidize the silicon when this material is reached during etching. The oxide layer formed on the silicon makes it possible to slow the etching of the silicon at the cost, however, of a surface conversion of the latter into oxide and thus of a silicon surface consumption. Helium serves as a diluent for oxygen. The advantage of this type of etching is that it is fairly anisotropic and allows to control sufficiently the profile of the spacers 150 even if one can not obtain in practice the ideal rectangular shape. The disadvantage of this type of etching is that the etch selectivity of the underlying silicon is however limited. The selectivity, that is to say the ratio of the etching rates between the silicon nitride and the silicon is of the order of 10 and can reach a maximum of 15 depending on the conditions of formation of the plasma (the nitride is etched 10 to 15 times faster than silicon).
    Also used are "wet" etchings based on hydrofluoric acid (HF) or phosphoric acid (H3PO4) which have a much better selectivity, respectively, with respect to silicon or its oxide (SiO 2) but which do not however make it possible to control the profile of the spacers since the etching is essentially isotropic in this case. Note that this type of engraving is also called "wet cleaning" translation of the English "wet clean".
    It will be noted here that there are numerous publications on the subject of the etching of silicon nitride and / or gate spacers in general. For example, reference can be made to the following US patents or applications: 2003/0207585; 4,529,476; 5,786,276 and 7,288,482.
    FIG. 1b illustrates a first problem which is related to the insufficient etching selectivity which exists during dry etching of the CH3F / 02 / He type between the silicon nitride and the silicon of the surface layer 146. The result is that a significant fraction of the thin surface layer of monocrystalline silicon 146 of the SOI substrate can then be partially consumed 147 during the anisotropic etching of the nitride. As previously mentioned, the surface layer 146 is chosen to be thin in order to improve the electrical characteristics of the transistors. It is typically less than 10 nm. The remaining thickness 145 may be very small. Under these conditions the ion implantation 105 to form the source and drain zones 110 which will follow is likely to be very damaging for the remaining monocrystalline silicon. The implantation energy of the dopants may be sufficient to cause complete amorphization 149 of the single-crystal silicon, which will then in particular compromise the next epitaxial growth step 112 intended to form the raised source / drain. As previously mentioned, this last operation is made necessary because of the size reduction of the transistors in order to be able to maintain the access resistances to the source and drain electrodes at sufficiently low values so as not to impact the electrical operation of the transistors. Growth from a partially or fully amorphous silicon layer will create many defects in the epitaxial layer.
    FIG. 1c illustrates another problem where there is no significant consumption of the silicon of the surface layer 146 but there is formation of "feet" 154 at the bottom of the remaining silicon nitride patterns on the sides of the gate after etching . The consequence is that the transition 114 of the junctions which are formed after ion implantation doping 105 of the source and drain zones 110, with the zone of the channel 130, is much less abrupt than when the spacers do not have feet as represented in FIG. previous figures. The presence of feet 154 affects the electrical characteristics of the transistors. It will be noted here that the formation or not of feet at the bottom of the spacers and the consumption or not of silicon of the silicon surface layer 146 of the SOI substrate, described in the previous figure, are antagonistic adjustment parameters of the etching which require that a compromise can be found for which, ideally, no feet are formed and the surface layer of silicon is not attacked significantly.
    Figure 1d illustrates a third problem that occurs when etching produces excessive erosion of the spacers in the upper portions of the grids and exposes the polysilicon 123 in these areas 156. The consequence is that the subsequent epitaxial growth 112 to form the raised source / drain will also occur at these locations, as well as silicidation of parasitic contacts, which may cause short circuits between electrodes. Indeed, the etching of the spacers requires that the etching time is adjusted to etch, for example, 150% of the deposited nitride thickness. That is, a 50% overgraft is performed in this example to account for the non-uniformity of the deposit, or the etching operation itself, at a wafer. Thus, in some parts of the slice we can see that there is a too sharp overgrading that exposes the grid areas 156. This type of defect is also called "faceting".
    In addition, for certain applications it may be necessary to provide a protective layer often based on carbon such as a mask or a photoresist (or "photoresist") or heat-sensitive to protect during the etching of spacers structures formed on the substrate. This is for example the case when producing PMOS transistors close to NMOS transistors whose spacers are in progress. The known methods of etching can lead to a high consumption of this protective layer during etching of the spacers of the PMOS transistor. Other solutions have been proposed in documents US2014 / 0273292 and FR12 / 62962. These solutions provide a step of implantation of a silicon nitride layer to modify it on either side of the gate, followed by a step of removing the modified silicon nitride layer.
    In the FR12 / 62962 solution, the step of removing the modified nitride layer can be carried out by wet cleaning using hydrofluoric acid (HF). The disadvantage is that wet HF cleaning does not allow selective removal of the modified nitride layer from the unmodified nitride layer. The selectivity to the unmodified nitride layer is, for example, 7 (for a 1% HF concentration).
    Moreover, hydrofluoric acid is a chemical compound, one of the main properties of which is to etch silicon oxide, so this method is intrinsically non-selective to the silicon oxide layer forming the hard mask as well as the trenches. of insulation (in English acronym STI for "shallow trench isolation"). The selectivity of this oxide layer to HF is, for example, 1 (for a concentration of HF of 1%).
    The object of the present invention is to propose a method for forming spacers which fully plays their role of isolation and which would eliminate or limit at least some of the defects in the production of transistors, such as the consumption or the alteration of the semiconductor material. conductive (ie Si, SiGe) of the active layer underlying the layer to be etched, the formation of "feet" at the bottom of the patterns on the sidewalls of the gate of a transistor, the consumption of a protective layer to carbon base, etc. The invention makes it possible to obtain spacers based on a dielectric material while reducing or even eliminating the problems of the known and previously mentioned solutions.
    Other objects, features and advantages of the present invention will become apparent from the following description and accompanying drawings. It is understood that other benefits may be incorporated.
    SUMMARY OF THE INVENTION
    To achieve this objective, one aspect of the present invention relates to a method of forming spacers of a gate of a field effect transistor, the gate having flanks and a top and being located above a layer. in a semiconductor material, the method comprising a step of forming a dielectric layer covering the gate of the transistor, the method comprising, after the step of forming the dielectric layer, at least one step of modifying said dielectric layer by bringing the dielectric layer into contact with a plasma which creates anisotropic light-ion bombardment in a preferred direction parallel to the sidewalls of the gate, the plasma conditions, in particular the light-ion energy and the implanted dose being chosen in order to modify, by implantation of the light ions, at least portions of the dielectric layer which are located on a top of the grill and and on either side of the grid and which are perpendicular to the sidewalls of the grid while retaining portions of the dielectric layer covering the unmodified or unmodified sidewalls of the grid over their entire thickness; the light ions being ions based on hydrogen and / or based on helium (He). The method also includes at least one step of removing the modified dielectric layer by selectively etching said layer-modified dielectric layer of a semiconductor material and against the unmodified dielectric layer.
    Advantageously, the step of removing the modified dielectric layer comprises a dry etching carried out by placing in the presence of a gaseous mixture, preferably solely gaseous, comprising at least a first component based on hydrofluoric acid (HF), the hydrofluoric acid transforming into non-volatile residues, preferably non-volatile at room temperature, the modified dielectric layer.
    Advantageously, the step of removing the modified dielectric layer comprises, only after the dry etching, a removal of non-volatile residues at room temperature by wet cleaning or sublimation thermal annealing.
    Particularly advantageously, the present invention allows a selective etching of the modified dielectric layer vis-à-vis a silicon oxide-based layer. The variation range of the parameters of the gaseous HF process making it possible to obtain a selectivity of the modified dielectric layer, for example based on silicon nitride (SiN) with respect to the unmodified dielectric layer, is more extensive.
    An advantage of the present invention is that the bringing into contact can be carried out in a simple chemical reactor: a hermetic enclosure in which the reactants are introduced and which operates either at room temperature and atmospheric pressure, or at a temperature higher than ambient and at a pressure below atmospheric pressure. The placing in the presence is therefore advantageously not performed in a plasma reactor whose equipment and management is more complex than a chemical reactor. Thus, the gaseous HF is simple to implement compared to a plasma. Indeed, a simple chemical reactor, possibly regulated in pressure and temperature, is sufficient. In the case of a plasma, it would take RF generators and work at a much lower pressure, so the equipment in this case would be much more complex.
    Advantageously, thermal annealing and HF etching are performed during successive and non-simultaneous steps. This makes it possible to prevent the temperature necessary for annealing to be harmful to the adsorption of HF on the surface of the plate, which would adversely affect the progress of the reaction between HF gas and the modified dielectric layer, for example based on SiN.
    In a particularly advantageous manner, the present invention not only allows a control of the damage that can be generated following an ion implantation, but also an improvement in the removal of the modified dielectric layer, by proposing a method having a better etch selectivity between the dielectric layer. modified and unmodified dielectric layer on the one hand, between the modified dielectric layer and the silicon oxide layer and between the modified dielectric layer and the layer of a semiconductor material, on the other hand. Advantageously, the selectivity of the HF gas process between the modified dielectric layer and the semiconductor material layer is infinite (that is, the HF gas does not etch the semiconductor material).
    Advantageously, the present invention provides an infinite selectivity of the modified dielectric layer. Thus, the present invention allows better control of critical dimensions. The method according to the present invention also allows a selective etching of the modified dielectric layer with respect to other unmodified layers for example, avoiding any risk of consuming all or part of a silicon nitride layer or a layer to silicon oxide base.
    In the present invention, the process is carried out sequentially. The etching, advantageously "dry", of the modified dielectric layer, for example of silicon nitride (SiN), is carried out using pure gaseous hydrofluoric acid (no co-injection of alcohol). At the end of the dry etching, non-volatile residues at room temperature (for example, in the form of salts) are present at the level of the modified dielectric layer.
    The term "salt" means an ionic solid compound formed of an anion and a cation but whose overall electrical charge is neutral.
    According to a first embodiment, the nonvolatile etching residues can then be eliminated by performing a simple wet cleaning with water. According to another preferred but non-limiting embodiment of the invention, in order to eliminate the non-volatile residues on the surface of the modified dielectric layer, an annealing is carried out after the "dry" etching of the modified dielectric layer. This annealing makes it possible to sublimate nonvolatile residues at room temperature, typically solid salts. This method can be used, for example, to replace a "wet" cleaning, for example water-based cleaning. Advantageously, this alternative method (pure gaseous HF followed by annealing) proposes an entirely "dry" process (which does not contain any steps in the liquid phase), which may be of interest for eliminating known problems caused by "wet" etchings. Made for the formation of patterns, for example.
    According to an advantageous embodiment, a prerecuit step is carried out before dry etching based on gaseous hydrofluoric acid. This makes it possible to eliminate the moisture naturally adsorbed on substrates and thus avoids introducing water, which is a proton acceptor, into the etching chamber of the etcher; said chamber comprising hydrofluoric acid (HF). Thus, the pre-annealing step makes it possible to further increase the selectivity between a modified silicon nitride (SiN) layer and a silicon oxide (SiO 2) layer.
    Particularly advantageously, no etching of a silicon oxide (SiO 2) layer can occur since the etching process of a silicon oxide-based layer only works with the simultaneous presence of silicon oxide. hydrofluoric acid and proton-accepting groups (such as alcohol, water). It is therefore by the absence of simultaneous introduction of hydrofluoric acid and proton acceptor groups, that a high selectivity between a modified silicon nitride (SiN) layer and an oxide layer is obtained. silicon (SiO2). This sequential process also shows a high selectivity between an unmodified silicon nitride (SiN) layer and a modified silicon nitride layer.
    Particularly advantageously, the sequential method according to the present invention offers a better selectivity of etching between silicon (Si) and silicon-germanium (SiGe), in particular by virtue of the intrinsic infinite selectivity of hydrofluoric acid towards these materials. This method also has a better etch selectivity between the silicon oxide (SiO 2) forming, for example, the hard mask and the unmodified silicon nitride (SiN), notably thanks to the absence of proton acceptor groups by using a process based on pure gaseous hydrofluoric acid. Other known solutions for removing a layer of modified SiN silicon nitride such as liquid phase hydrofluoric acid (HF) or phosphoric acid (H3PO4) do not allow such selectivity towards, respectively, silicon oxide. (SiO2) or unmodified silicon nitride (SiN).
    Advantageously, the parameters of the step of removing the modified dielectric layer, in particular the ratio of gas between the first component and the second component used during the dry etching, are provided so that the modified dielectric layer can be etched selectively with respect to the layer of a semiconductor material and vis-à-vis the unmodified dielectric layer and, advantageously, vis-à-vis the silicon oxide layer. It is therefore important to find a fair ratio between the content of first component and second component during dry etching to remove the modified dielectric layer. Advantageously, the ratio of gas between the first component (for example, HF gas) and the second component (for example, pure N2) is between 1: 25 and 1: 1.
    A lower ratio, which would be the case if the flow rate of the first component is reduced, would have the consequence of limiting the efficiency of the etching of the modified dielectric layer. A higher ratio, which would be the case if the flow rate of the first component is increased, would have the effect of limiting the selectivity with respect to the unmodified silicon nitride layer and with respect to the silicon oxide layer. In the present patent application, the ratio between two gaseous components is understood to mean a ratio relating to the respective rates of introduction of the components into the chamber of the chemical reactor (when using gaseous HF). Each flow is usually measured in cubic centimeters per minute (sccm). Typically a flow rate is measured with a flow meter associated with each flow of gas entering the reactor.
    Advantageously, the dry etching consumes the modified dielectric layer preferentially to the layer made of a semiconductor material and to the unmodified dielectric layer. Thus, the risk of excessive consumption of the surface layer of semiconductor material is reduced or even eliminated.
    According to a preferred embodiment, the etching of the dielectric layer is carried out using a carbon-free chemistry. This advantageously avoids the deposition of a carbonaceous layer that can hinder the etching of the dielectric layer.
    Optionally, the method may further have at least any of the features and steps below. Preferably, the HF gas is available in a bottle and can therefore be directly injected into the reactor after expansion at the pressure at which the reactor operates. The gaseous HF can also be generated by evaporation of liquid HF and driven by a stream of nitrogen (N2) to the reactor. The gaseous HF, whichever of the above methods is used, is preferably mixed with a stream of pure nitrogen to control the HF concentration in the reactor. This mixture between gaseous HF and pure N2 is carried out either in situ in the reactor or upstream of the reactor in a mixing chamber. the step of removing the modified dielectric layer comprising a removal of the non-volatile residues by a wet cleaning or a sublimation thermal annealing is carried out exclusively after the dry etching step. Wet cleaning or sublimation thermal annealing is not performed during the dry etching step. The parameters of the step of removing the modified dielectric layer, in particular the ratio of gas between the first component and the second component used during dry etching, are provided so that the modified dielectric layer can be etched with selectively towards the layer of a semiconductor material and vis-à-vis the unmodified dielectric layer. - The first component is generated by evaporation from a liquid source or from a pressurized bottle. - The placing in presence is carried out in a chemical reactor. - The reactor comprises an enclosure. The bringing into contact is carried out at room temperature and atmospheric pressure or is carried out at a temperature above ambient temperature and at a pressure below atmospheric pressure. - The first component consists only of HF. The gaseous mixture comprises a second component based on an inert gas chosen from nitrogen (N 2) and / or argon (Ar). - The ratio of gas between the first component and the second component is between 1: 25 and 1: 1. Dry etching is carried out at a temperature of between 15 ° C. and 80 ° C., a pressure of between 40 Torr and 760 Torr, for a duration ranging from a few seconds to a few minutes. - Removal of non-volatile residues is performed after dry etching. The removal of non-volatile residues comprises an annealing carried out at a temperature of between 200 ° C. and 400 ° C. - The annealing is performed under a low pressure between 10.10'3 Torr and 2 Torr. - The annealing is performed for a time between 60 and 600 seconds. - Removal of non-volatile residues includes wet cleaning with de-ionized water. - Prior to the step of removing the modified dielectric layer, thermal annealing under vacuum, at a temperature above 100 ° C. - The dielectric layer is formed of one or more dielectric materials whose dielectric constant k is less than or equal to 7. - The dielectric layer is a nitride layer. - The dielectric layer is a layer based on silicon (Si). The material of the dielectric layer is taken from: SiCO, SiC, SiCN, SiON, SiOCN, SiCBN, SiOCH, and SiOx, for example SiO 2. - The semiconductor material is silicon and the step of removing the modified dielectric layer is performed in part at least by dry etching selectively silicon (Si) and / or silicon oxide (SiO 2). A single modification step is performed so as to modify the dielectric layer throughout its thickness on all the surfaces parallel to the plane of a substrate on which the grid rests and not to modify the dielectric layer throughout its thickness on the surfaces. perpendicular to this plane. The layer made of a semiconductor material is taken from: silicon (Si), germanium (Ge), silicon-germanium (SiGe) and in which the light ions are taken from helium (He) and / or hydrogen (H2) and / or ammonia (NH3). - The light ions are based on hydrogen and the flow rate of the light ions based on hydrogen (H) is between 10 and 500 sccm (cubic centimeter per minute), the hydrogen-based ions (H) being taken among: H, H +, H2 +, H3 +. The light ions are based on helium and the flow rate of the light ions based on helium (He) is between 50 and 500 sccm. The step of modifying the dielectric layer is carried out with a polarization power or source power of between 20 V (volts) and 500 V, with a pressure of between 5 mTorr (milliTorr) and 100 mTorr, at a temperature between ° C and 100 ° C, for a period of a few seconds to a few hundred seconds. The step of modifying the dielectric layer made from a plasma modifies the dielectric layer continuously from the surface of the dielectric layer and over a thickness of between 1 nm (nm) and 30 nm, preferably between 1 nm and 10 nm. The transistor is a FDSOI type or FinFET type transistor.
    BRIEF DESCRIPTION OF THE FIGURES
    The objects, objects, as well as the features and advantages of the invention will become more apparent from the detailed description of an embodiment thereof which is illustrated by the following accompanying drawings in which:
    FIGS. 1a to 1d show, on the one hand, a sectional view of an exemplary MOSFET transistor of the FDSOI type in progress, and, on the other hand, illustrate various defects that can be observed on FDSOI transistor structures. when etching the spacers using either of the standard anisotropic etching processes developed by the microelectronics industry.
    FIGS. 2a to 2d illustrate the steps of an exemplary method according to the invention applied to the production of transistors of the FDSOI type.
    FIG. 3 illustrates a graph showing the etching rate of a silicon oxide layer as a function of the percentage of alcohol present.
    FIG. 4 summarizes the steps of an exemplary method of the invention intended to form spacers and which do not induce or at least limit the defects described in FIGS. 1b to 1d.
    The accompanying drawings are given by way of example and are not limiting of the invention. These drawings are schematic representations and are not necessarily at the scale of the practical application. In particular, the relative thicknesses of the layers and substrates are not representative of reality.
    DETAILED DESCRIPTION OF THE INVENTION
    It is specified that in the context of the present invention, the term "over", "overcomes" or "underlying" or their equivalent do not necessarily mean "in contact with". For example, the deposition of a first layer on a second layer does not necessarily mean that the two layers are in direct contact with one another, but that means that the first layer at least partially covers the second layer. being either directly in contact with it or separated from it by another layer or another element.
    In the following description, the thicknesses are generally measured in directions perpendicular to the plane of the lower face of the layer to be etched or a substrate on which the lower layer is disposed. Thus, the thicknesses are generally taken in a vertical direction in the figures shown. On the other hand, the thickness of a layer covering a flank of a pattern is taken in a direction perpendicular to this flank.
    FIGS. 2a to 2d describe the steps of a detailed example of a method according to the invention applied to the production of FDSOI type transistors. The principles of these steps can also be applied to the formation of spacers on the flanks of a gate of another type of transistor.
    FIG. 2a illustrates the step of depositing a dielectric layer 152, preferably of substantially uniform thickness, on all the surfaces, vertical and horizontal, of the devices being manufactured. This step is preferably carried out using a deposition method known as LPCVD, the acronym for "low pressure chemical vapor deposition", that is to say "low pressure chemical vapor deposition". . This type of deposit which is practiced under atmospheric pressure allows indeed a uniform deposit on all surfaces regardless of their orientation.
    Although this is not necessary for understanding the method of the invention, it will be noted that in this example the gate electrode is composed at this stage of the multi-layer method for certain types of transistors. In addition to the polycrystalline silicon layer 123, there is, in the stack of layers forming the grid 120, first of all the thin insulating layer of gate oxide 121 through which an electric field will be able to develop to create the channel 130 of conduction between source and drain, when a sufficient voltage is applied to the grid. In the most recent MOSFET transistors, it is implemented a qualified technology of the English term "high-k / metal spoils" that is to say that the insulating layer 121 is made of an insulating material with high permittivity (high-k) covered by a metal grid (metal spoil) represented by the layer 122. This technology was developed in particular to reduce the leakage currents through the grid which became much too important due to the decrease in thickness insulating layer 121 to atomic dimensions. At this point, the stack of layers of the grid also comprises a hard mask 124 of protection which will be removed later to allow the resumption of contact on this electrode. This hard mask, which remains in place after etching the gate, is typically made of silicon oxide (SiO 2). Its role is to protect the top of the grid from any damage during the engraving of the spacers.
    Preferably, the insulating layer 121 is disposed in contact with the layer 146 of a semiconductor material forming the conduction channel. Preferably, the layer 122 is disposed in contact with the layer 121. Preferably, the layer 123 is disposed directly in contact with the gate oxide formed by the layer 121, if the layer 122 is absent or is disposed directly in contact of the layer 122. Preferably, the dielectric layer 152 is disposed directly in contact with the layer 123 at the sidewalls of the gate. Preferably, the dielectric layer 152 is disposed directly in contact with the layer 146 of a semiconductor material for forming the conduction channel.
    According to one embodiment, the dielectric layer 152 is based on nitride. According to one embodiment, the nitride dielectric layer 152 has a thickness of between 5 and 20 nm, and typically of the order of 10 nm. By way of example, the dielectric layer 152 is based on silicon nitride (SiN). The dielectric layer 152 may also be chosen from silicon oxycarbide (SiCO), silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), SiCBN, oxycarbide of silicon hydrogenated silicum (SiOCH) and silicon oxide SiOx with x greater than or equal to 1 such as SiO 2.
    According to another embodiment, the dielectric layer 152 comprises a low-permittivity dielectric material ε (the permittivity is denoted epsilon) or a low dielectric constant k, with preferably k less than or equal to 7. Thus, the present invention does not is not limited to a dielectric layer formed based on nitride. The present invention is also not limited to a dielectric layer of silicon nitride (SiN).
    The present invention advantageously extends to any spacer comprising a dielectric material with low permittivity ε (called "low-k" in English). The term "permittivity of a material", at the microscopic level, the electric polarizability of the molecules or atoms constituting said material. The permittivity of a material is a tensor quantity (the response of the material may depend on the orientation of the crystallographic axes of the material), which is reduced to a scalar in isotropic media. The dielectric constant is denoted k in the field of integrated circuits and semiconductors, for example. The so-called "low-k" materials are dielectrics with low permittivity. They are used as insulators between metal interconnects to reduce the coupling between them.
    In one embodiment, the dielectric layer 152 has or comprises a material having a dielectric constant of less than 4 and preferably less than 3.1 and preferably less than or equal to 2, thereby reducing the parasitic capacitance to possibly improve the transistor performance. For example, as indicated above the material of the dielectric layer 152 is taken from: SiCO, SiC, SiCN, SiOCN, SiON, SiCBN, SiOCH and SiOx with x greater than or equal to 1 as for example SiO2. This reduces the parasitic capacitance and consequently improves the performance of the transistor.
    Preferably, but only optionally, the method of the invention comprises an optional step of reducing the dielectric constant of the dielectric layer 152. According to an advantageous embodiment, the reduction of the dielectric constant is obtained during the step of depositing the dielectric layer 152.
    According to one embodiment, the reduction of the dielectric constant comprises the introduction into the dielectric layer 152 in forming precursors which form bonds reducing the polarizability of the dielectric layer 152. These precursors are chosen so as to generate less polar bonds as silicon nitride, such as Si-F, SiOF, Si-O, CC, CH, and Si-CH3.
    According to another embodiment, alternative or combinable with the previous one, the reduction of the dielectric constant comprises the introduction into the dielectric layer 152 forming a porosity.
    FIG. 2b illustrates the following step of the invention applied to the production of FDSOI transistors in which a modification 430 of the dielectric layer 152 that has just been deposited is carried out directly. Optionally, this operation may have been preceded by a "main" etching 420, for example a conventional dry etching of type CH3F / 02 / He. The modification step 430 of the dielectric layer 152 as deposited, or of the layer remaining after a first conventional etching, is by implantation 351 of light species also designated light ions. In the context of the present invention, these ions are ions based on hydrogen (H) and / or based on helium (He).
    The hydrogen-based ions (H) are for example taken from: H, H +, H2 +, H3 +.
    Advantageously, these species can be taken alone or in combination. For example, the possible chemistries for implantation are: H, He, NH3, He / H2, He / NH3. These ions can be implanted in a material to be etched, without causing dislocation of its atomic structure such that it would cause a spray of the latter.
    The term "light ions" means ions from materials whose atomic number in the periodic table of elements is low. In a general way all the elements that can be implanted in the material to be engraved, without causing dislocation of its atomic structure such that it would result in a spraying of the latter, and therefore without re-deposition of the material etched on the reactor walls or the patterns being etched themselves, are likely to agree.
    Particularly advantageously, the implantation of light species is favored by the incorporation into the plasma of a second component allowing the dissociation of the light ions and therefore the increase in the density of light ions in the plasma and the plasma. increase of the implanted dose.
    Advantageously, the implantation parameters, in particular the energy imparted to the ions, the duration and the implantation dose are provided so that the modified dielectric layer 158 can be etched selectively with respect to the layer 146 in a semiconductor material. driver.
    Advantageously, these parameters are also adjusted so that the modified dielectric layer 158 can be etched selectively with respect to the unmodified portion of the dielectric layer 152.
    Advantageously, these parameters are also adjusted so that the modified dielectric layer 158 can be etched selectively with respect to a layer made of an oxide, typically an oxide of said semiconductor material, the latter forming for example an oxide layer grid. Typically, the etching is selective of the modified dielectric material by implantation of hydrogen vis-à-vis the silicon oxide. Implantation is carried out, according to a non-limiting example of the invention, in a plasma based on hydrogen gas (H2). More generally, all the gaseous components, which can dissociate the light ions mentioned above, can be used in the plasma. It will be noted here that this modification step 430 of the dielectric layer 152 to be etched can be practiced in many different ways by adapting all kinds of means commonly used by the microelectronics industry. In particular, standard etching reactors are used in which low or high density plasmas can be produced and where the energy of the ions can be controlled to allow the implantation of the light species above intended to modify the layer to be etched. It is also possible to use a type of so-called immersion plasma commonly used for practicing implantation of species on the surface of a device during manufacture. Finally, implantation can also be done in a standard implanter where the ions are accelerated in an electric field to obtain their implantation in a solid. The modification operation is advantageously very anisotropic for the production of the spacers on the sidewalls of the grids because of the directionality of the ions of the plasma or the implanter. It therefore preferably affects the horizontal surfaces, that is to say all the surfaces parallel to the plane of the substrate 142. The thickness modified on the horizontal surfaces 154 is thus much larger than on the vertical surfaces 156 that is to say on all surfaces perpendicular to the plane of the substrate 146 developed, on which is arranged the grid. Advantageously, the implantation according to the present invention makes it possible not to attack the vertical surfaces. Thus, according to a preferred embodiment, the modified thickness on the vertical surfaces 156 is almost zero, preferably of the order of 1 to 3 nanometers.
    This plane is perpendicular to the plane of the section shown in Figures 2a to 2d. The prepared substrate 142 preferably forms a plate (or "wafer" in English) with two parallel faces. It is for example in the form of a disk, a square, a polygon, etc. The thin layer 146, the buried oxide layer 144 and the solid substrate 142 are arranged in parallel planes. Thus, a surface will be described as horizontal if it is parallel to the plane of the layer or layers forming the substrate 146, on which the grid is formed and a surface will be described as vertical if it is perpendicular to the same plane.
    Typically, a thickness 154 of 10 nm on the horizontal surfaces can be changed during this operation. A thickness 156 of the layer 152 ranging from 1 to 3 nm is however also modified on the vertical surfaces regardless of the plasma conditions. These vertical surfaces with respect to the plane of the substrate 146 are therefore parallel to the sides of the grid. The modified thicknesses depend on the conditions of implementation, in particular on the means employed (plasma or implanter) and also on the fact that it is desired to obtain the etching of the spacers in a single overall step of modification and etching, or that on the contrary repeat these operations until you obtain a complete engraving.
    Thus, depending on the particular implementations of the method of the invention and the initial thickness of the dielectric layer 152, the step of modifying this layer can affect the whole of this layer where, as represented in the example of Figure 2b, only part of it. In this particular case, the material is modified over its entire thickness but only at the level of the horizontal zones 154. In this case, the modification step 430 and the following step 440 of the withdrawal of the modified layer described below may be repeated until complete removal of the dielectric material from the modified dielectric layer 158 on all horizontal surfaces. Plasma implantation has the advantage of allowing implantation to be continuous in a volume extending from the surface of the implanted layer. In addition, the use of plasma allows implantation at lower depths than the minimum depths that can be achieved with implants. Thus, a plasma implantation makes it possible to implement efficiently and relatively homogeneously or at least continuously thin layers that can then be removed by selective etching. This continuity of implantation from the implanted face makes it possible to improve the homogeneity of the modification according to the depth, which leads to a constant etching rate in the time of the implanted layer. Moreover, the increase of the selectivity conferred by the implantation with respect to the other layers is effective from the beginning of the etching of the implanted layer. The plasma implantation thus allows a significantly improved control of the engraving accuracy. Plasma implantation typically allows implanting and then removing thicknesses extending from the surface of the implanted layer and at a depth of 0 nm to 100 nm. Traditional implanters allow implantation in a volume between 30 nm and several hundred nanometers. On the other hand, conventional implanters do not make it possible to implant the species between the surface of the layer to be implanted and a depth of 30 nm. In the context of the development of the present invention, it has been noted that the implanters do not then make it possible to obtain a sufficiently constant etching rate of the modified layer from the surface of the latter, thus leading to a lower precision of engraving compared to what the invention allows. The use of a plasma to modify the layer to be removed is therefore particularly advantageous in the context of the invention which aims to remove a thin layer of a dielectric layer 152, typically between 1 and 10 nm and more generally between 1 and 10 nm. and 30 nm. The modification step made from a plasma modifies the dielectric layer 152 continuously from the surface of the dielectric layer 152 and over a thickness of between 1 nm and 30 nm and preferably between 1 nm and 10 nm.
    According to a particularly advantageous embodiment, the modification 430 by implantation of the dielectric layer 152 and the withdrawal 440 of the modified dielectric layer 158 are made in the same equipment: the modification in a plasma reactor and the withdrawal in a chemical reactor with HF gaseous. The modification of the dielectric layer 152 to be removed by plasma implantation thus makes it possible to modify the dielectric layer 152 and the dry etching in the same chamber of the modified dielectric layer 158 which is very advantageous in terms of simplification , time and cost of the process.
    Particularly advantageously, the modification of the dielectric layer 152 by implantation of light ions, hydrogen-based ions (H), makes it possible to considerably improve the selectivity of this modified dielectric layer 158 with respect to the layer 146 by a semiconductor material, typically silicon. This implantation also causes the thickness of the modified dielectric layer 158 to be etched more rapidly than that of the unmodified dielectric layer 152.
    Preferably, the modification of the dielectric layer 158 retains an unmodified dielectric thickness 152 on the sidewalls of the gate. This thickness is preserved, at least in part, during the selective etching. It then defines grid spacers.
    Preferably, the parameters of the implantation, in particular the implantation energy of the light ions originating from the first component and the implanted dose, are provided so that the modified dielectric layer 158 can be etched selectively with respect to of the material of the layer 146 in a semiconductor material and vis-à-vis the unmodified dielectric layer 152.
    Preferably, a single modifying step is performed so as to modify the dielectric layer 152 throughout its thickness on all the surfaces parallel to the plane of a substrate on which the grid rests and not to modify the dielectric layer 152 in all its thickness on the surfaces parallel to the preferred direction of implantation.
    Advantageously, the implantation is performed so as to modify the entire thickness of the dielectric layer 152 outside the dielectric layer 152 disposed on the sides of the gate. Thus, the shrinkage 440 (advantageously comprising a dry etch 441 and a surface removal of residues 442) removes all the modified dielectric layer 158 except for at least a portion of the unmodified dielectric layer 152 located on the flanks. Grid.
    Advantageously, the implantation modifies the dielectric layer 152 from its surface and to a depth corresponding to at least part of its thickness. Preferably, the implantation modifies the dielectric layer 152 uninterruptedly from the surface.
    According to a particular embodiment, the method comprises a single modification step 430 performed so as to modify the dielectric layer 152 throughout its thickness on all the surfaces parallel to the plane of a substrate on which the grid rests and not to modify the dielectric layer 152 throughout its thickness on the surfaces perpendicular to this plane. These surfaces perpendicular to this plane, that is to say perpendicular to the layer 146 of a semiconductor material forming a conduction channel or solid substrate are typically parallel to the sides of the gate of the transistor. Thus, following this single modification step 430, a recess 440 (advantageously comprising a dry etching 441 and a removal of residues 442 at the surface) selective of the modified dielectric layer 158 makes it possible to remove the dielectric layer on all the surfaces except on those parallel to the sides of the grid.
    According to another embodiment, the method comprises several sequences each comprising a modification step 430 and a withdrawal step 440. During at least one of the modification steps 430, only a part of the thickness of the dielectric layer 152 is modified. Advantageously, the sequences are repeated until the dielectric layer 152 disappears on all the surfaces parallel to the plane of a substrate on which the grid rests. Only the faces parallel to the sidewalls of the grid retain a dielectric thickness, this thickness has not been modified by implantation.
    According to an advantageous embodiment, the dielectric layer 152 is disposed directly in contact with the layer 146 of a semiconductor material. Preferably the dielectric layer 152 is disposed directly in contact with the gate which is preferably formed of a semiconductor material.
    Advantageously, the implantation, in particular its energy, the concentration and the nature of the light ions, the dose used and the duration of the implantation process, are provided so that the modified dielectric layer 158 can be etched selectively vis-à-vis -vis the rest of the dielectric layer, that is to say the unmodified dielectric layer 152.
    FIG. 2c illustrates the final result of the following step after etching, that is to say the removal 440 of the modified dielectric layer 158 and possibly repeated, on the one hand, the modification operation described in the previous figure, and on the other hand, the operation of removing the modified dielectric layer 158.
    According to one embodiment, prior to the removal of the modified dielectric layer, a (pre-) annealing 443 is carried out at atmospheric pressure or under vacuum, at a temperature preferably greater than 100 ° C. in order to eliminate all the moisture on the surface of the plate. The waiting time between the pre-annealing 443 and the dry etching 441 based on hydrofluoric acid (HF) gas must be kept to a minimum. By way of preference, the pre-annealing 443 and the dry etching 441 based on hydrofluoric acid HF must be carried out in the same tool.
    The method according to the present invention comprises a removal of the modified dielectric layer 158 consisting, as already mentioned, of resorting to a sequence of steps. A first step comprising a dry etching 441 carried out by placing in the presence of a gaseous mixture comprising at least a first component based on hydrofluoric acid (HF) and a second stage comprising a removal of non-volatile residues 442 present on the surface of the plate (and in particular on the surface of the modified dielectric layer 158).
    Dry etching 441 is preferably carried out in an etching tool capable of injecting both gaseous hydrofluoric acid (generated either by evaporation from a liquid source or from a pressurized bottle) and inert gas (eg nitrogen (N2) or argon (Ar)) to control the hydrofluoric acid concentration in the reactor chamber and therefore the etch rate. The flow rates for each gas flow must preferably be independently controlled. The tool can be used to engrave both a single plate and a lot of plates. The etching tool can advantageously operate at ambient pressure and temperature and / or at low pressure and / or at high temperature.
    The bringing into contact is preferably carried out in a simple chemical reactor: a hermetic enclosure in which the reactants are introduced and which operates either at ambient temperature and atmospheric pressure, or at a temperature higher than ambient and at a pressure below atmospheric pressure. . The placing in the presence is advantageously not made in a plasma reactor, which would have no advantage over the simple chemical reactor. The gaseous HF is available in bottle and can therefore be directly injected into the reactor after expansion at the pressure at which the reactor operates. H F gas can also be generated by evaporation of liquid HF and driven by a flow of nitrogen to the reactor. The gaseous HF, whichever of the above methods is used, is mixed with a stream of pure nitrogen to control the HF concentration in the reactor. This mixture between gaseous HF and pure N2 is carried out either in situ in the reactor or upstream of the reactor in a mixing chamber.
    The dry etching 441 advantageously makes it possible to remove a thickness of the modified dielectric layer 158 between 1 nanometer and a few tens of nanometers. Preferably, the gaseous mixture used during the dry etching comprises a second component. The second component is preferably an inert gas, for example selected from nitrogen or argon. The use of an inert gas makes it possible to avoid any other parasitic chemical reaction which could adversely affect the etching selectivities of the other materials (unmodified SiN, SiO 2, semiconductor). Advantageously, the second component makes it possible to control the concentration of HF. The second component, preferably an inert gas, allows dilution to the desired concentration of HF. In the case of the use of pure HF, selectivity to silicon oxide would be lost.
    The parameters of the dry etching 441, and in particular the ratio of gas between the first component and the second component, are provided so that the modified dielectric layer 158 can be etched selectively with respect to the layer 146. in a semiconductor material and vis-à-vis the unmodified dielectric layer 152.
    Preferably, the gas ratio between the first component and the second component is between 1: 25 and 1: 1. The first component is advantageously based on hydrofluoric acid and the second component is advantageously based on an inert gas. Preferably, the inert gas (the second component) is selected from argon (Ar) and nitrogen (N2). The inert gas content is configured to adjust the ratio and, therefore, the etch rate. Advantageously, nitrogen is preferred to argon for a less expensive method of production. The dry etching is preferably carried out at a temperature of between 15 ° C. and 80 ° C., a pressure of between 40 Torr and 760 Torr, for a duration ranging from a few seconds to a few minutes (depending on the thickness of the layer modified dielectric 158 to be removed).
    The dry etching converts the modified dielectric layer 158 into non-volatile residues or solid salts. Advantageously, the HF gas is available in a bottle and can therefore be directly injected into the reactor after expansion at the pressure at which the reactor operates. The gaseous HF can also be generated by evaporation of liquid HF and driven by a flow of nitrogen to the reactor. The gaseous HF, whichever of the above methods is used, is mixed with a stream of pure nitrogen to control the HF concentration in the reactor. This mixture between gaseous HF and pure N2 is carried out either in situ in the reactor or upstream of the reactor in a mixing chamber.
    Advantageously, a withdrawal 442 of non-volatile residues is carried out in order to remove any non-volatile residue present on the surface of the plate and formed during the dry etching. Advantageously, the dissolution of the non-volatile residues in the form of solid salts is only formed on the volume of the material of the modified dielectric layer 158.
    Advantageously, the removal 442 of non-volatile residues is carried out after dry etching 441 so as to sublimate the residues formed during the dry etching 441 based on hydrofluoric acid gas. In this embodiment, the removal of non-volatile residues can, according to an alternative, comprise a thermal annealing performed at a low pressure of between 10 × 10 -3 Torr and 2 Torr. According to a non-limiting example of the invention, the annealing is carried out in an environment comprising nitrogen and hydrogen (4%), at a temperature of 200 ° C., under a pressure of 1.5 Torr, the flow rate of which is 2000 sccm, for a duration of 180 seconds. Particularly advantageously, at the end of this removal step 442 of non-volatile residues, the residues are volatilized, leaving a surface free of any residue.
    Alternatively, removal 442 of nonvolatile residues may include wet deionized water cleaning. To do this, according to a non-limiting embodiment, the wafer is immersed in a bath comprising deionized water, for a period of about 10 minutes, with recirculation of the flow. According to another embodiment, the surface of the wafer or batch of wafers is sprayed with a spray comprising a solution of deionized water. Particularly advantageously, at the end of this step of removing non-volatile residues, the residues are solubilized, leaving a surface free from any residue. Stopping the etching is done on the unmodified dielectric layer 152 or on the monocrystalline silicon of the layer 146 or on the hard mask 124 at the top of the grids. It will be noted here, with reference to the problem described in FIG. 1b, that there is no silicon consumption due to the use of hydrofluoric acid. Furthermore, an optimization of the modification step 430 by implantation of light species described above entails only a modification of the dielectric layer 152 and the subsequent etching operation does not therefore affect the silicon under -jacent. Thus, as shown, there is very advantageously no consumption in the S / D zones 110 of the silicon layer 146. At the end of these operations, only the vertical patterns remain from the initial dielectric layer 152. essentially on the flanks of the stack of layers forming the gate 120. They constitute the gate spacers 150 of the transistor.
    FIG. 2d illustrates the formation of the drain and source zones of a FDSOI type transistor. At the end of the last or only step of removing the modified dielectric layer 158, that is to say when it has been removed on all the horizontal surfaces, a cleaning operation called " wet cleaning "most often qualified by its English term" wet clean ". As already noted previously wet etching and wet cleaning are similar operations that can be advantageously combined in a single operation.
    It is then possible to proceed with the formation of the source and drain electrodes 110. As already mentioned, the doping which will delimit the source and the drain and therefore the length of the channel 132 can be done by ion implantation before the epitaxially grow on these areas in order to increase their cross-section and decrease their resistance. If the doping is carried out before epitaxial growth, as shown in FIG. 2d, the process is said to be an English term "first extension" used to indicate that the extensions (of source and of drain under the spacers) are carried out first, that is, before epitaxial growth. In the opposite case which is said to be "extension last", one proceeds directly to the epitaxial growth step without prior doping. The doping of the source / drain zones is done only after epitaxial growth of these zones. In the case of n-channel transistors (nMOS), the implanted dopants are typically arsenic (As) or phosphorus (P). For p-channel transistors (pMOS) the dopants are boron (B) or boron difluoride (BF2).
    The result is illustrated in FIG. 2d which shows the doped source / drain zones 114 before epitaxial growth of the raised source / drain zones 116.
    Advantageously, the gate of the transistor is located on a stack of layers forming an elaborate silicon-on-insulator (SOI) substrate. Preferably, it is disposed directly in contact with the layer forming the conduction channel. Advantageously, the use of the invention with such an SOI substrate makes it possible to preserve the integrity of the superficial layer of very thin thickness which forms the conduction channel of a transistor formed from an SOI substrate.
    Advantageously, the semiconductor material is silicon. Advantageously, the etching is selective with silicon oxide (SiO 2). The semiconductor material may also be germanium (Ge) or silicon-germanium SiGe. The step of removing the modified dielectric layer is performed by etching, preferably with the aid of HF gas; which makes it particularly advantageous to selectively etch Ge or SiGe and / or SiGe oxide or Ge oxide.
    According to one embodiment, the transistor is a FDSOI type transistor. Preferably, the method comprises a step of completely removing the dielectric layer outside the sidewalls and on both sides of the grid to expose the layer in a semiconductor material and a source zone forming step drain from the layer into a semiconductor material, for example by epitaxy.
    FIG. 3 illustrates a graph representing the etching rate of a silicon oxide layer as a function of the percentage of alcohol present in the gas stream introduced into the etching reactor. Gaseous mixture etching processes from hydrofluoric acid have been developed mainly to perform etchings of microelectromechanical devices (MEMS acronym for "Micro-Electro-Mechanical Systems"), where a layer of The sacrificial silicon oxide must be removed by an isotropic process. The process, based on hydrofluoric acid (HF) in the gas phase, has great advantages compared to a process based on hydrofluoric acid (HF) in the liquid phase. In particular, using a gas phase process eliminates the capillary forces that are established between a solid surface and a liquid phase. In particular, in the case of MEMS, the capillarity forces can cause the surfaces of the fixed and moving parts of the device to come closer together, such that permanent forces are then established (for example, the Van Der Waals force) immobilizing the moving part and making the non-functional device. This is called "collage" ("stiction" in English), which the HF gas process largely avoids.
    Gaseous mixture etching processes from hydrofluoric acid have also been evaluated for cleaning prior to an epitaxy step for FEOL type devices. However, these so-called "dry" cleanings (for example, based on gaseous hydrofluoric acid) have not demonstrated a superior performance to the so-called "wet" traditional cleanings (for example, based on liquid hydrofluoric acid) and do not have not been widely adopted.
    To proceed with the etching of a silicon oxide (SiO 2) layer by HF hydrofluoric acid molecules, proton acceptor groups are required. In the case of hydrofluoric acid in the liquid phase, water (H 2 O) naturally plays this role. In the case of hydrofluoric acid in the gaseous phase, hydroxyl groups are added to the incoming gas flow by coinjection of alcohol vapors (methanol, ethanol or isopropanol are most commonly used) in the burner chamber with gaseous hydrofluoric acid. The methods used for engraving MEMS devices work this way. Without co-injection of alcohol, the etching rate of the silicon oxide is extremely low as shown in FIG. 3. The abscissa represents the concentration of co-injected alcohol, for example ΓΙΡΑ (Isopropyl alcohol). ) with gaseous hydrofluoric acid and the y-axis represents the etching rate (in Angstrom / minute).
    It is observed that the lower the percentage of alcohol and thus of proton acceptor groups at the surface, the lower the etching rate of the silicon oxide layer (in other words, the less the SiOx layer is etched). On the contrary, the more the percentage of alcohol increases, the more the etching rate increases favoring the etching of the silicon oxide layer.
    Thus, to limit the etching of a silicon oxide layer, it is necessary to avoid simultaneously bringing into contact the hydrofluoric acid and the alcohol (ie the proton acceptor groups).
    Advantageously, the process according to the present invention, by proposing a sequence of successive steps (on the one hand, a removal 442 of nonvolatile residues on the surface and, on the other hand, a dry etching 441 based on hydrofluoric acid) avoids the simultaneous presence of hydrofluoric acid and proton acceptor groups (such as alcohol, water), and thus allows selective etching of the modified dielectric layer 158 with respect to a silicon oxide layer (the etching of which will be limited).
    FIG. 4 summarizes the steps of the method of the invention intended to form spacers and which do not induce any of the defects described in particular in FIGS. 1b, 1c and 1d for the production of transistors, for example FDSOI.
    After depositing LPCVD with a uniform dielectric layer 152 on all the surfaces of the devices being manufactured, said modified dielectric layer 158 is removed on the surfaces that are not intended to form the spacers. This removal comprises several steps, including steps 430, 440 and optionally step 420 beforehand.
    Thus, optionally, a "main" etching is performed, preferably anisotropic conventional dry etching 420 of the modified dielectric layer 158. This is typically carried out in a plasma type CH3F / 02 / He described above. In the context of specific implementations of the invention, it is possible to decide whether or not to maintain the main etching step 420, the following steps then apply either to the dielectric layer 152 as filed or to the layer remaining after that a main etching was previously performed as in the standard method of etching the spacers.
    As shown in FIG. 2b, the following step 430 consists in anisotropically modifying all or part 154 of the remaining dielectric layer 152 by implantation of light ions. Advantageously, the second component interacts with the first component to dissociate the first component and promote the creation of light ions, thereby increasing the concentration of H ions and the dose.
    Depending on the applications of the process of the invention, it may be preferred to use a plasma etcher for plasma implantation, in particular for the following reasons: the cost of the apparatus is lower, the manufacturing cycle times may be shorter since the main etching step 420 and that of modification 430 of the dielectric layer 152 can then be done in the same apparatus without releasing devices in the process of manufacture. It will be noted in particular that the modification step 430 can be practiced in many different ways by adapting all kinds of means commonly used by the microelectronics industry, such as using any type of burner, for example in a ICP reactor of the English "Inductively Coupled Plasma" that is to say "inductively coupled plasma", or in a type of reactor CCP of the English "Capacitively Coupled Plasma" that is to say "plasma Capacitive coupling "which controls the energy of the ions. It is also possible to use a type of so-called immersion plasma commonly used for practicing implantation of species on the surface of a device during manufacture.
    In order to choose the implantation parameters, the person skilled in the art, in order to determine the behavior of the material to be etched in the type of plasma etcher chosen, will preferentially proceed to "full-plate" tests in order to establish behavior curves. He will deduce the parameters of the implantation, in particular the energy and the dose of ions, that is to say the exposure time, to use to reach the desired thickness of material to be modified. The next step 440 is that in which etching of the modified layer or at least the modified thickness of the modified dielectric layer 158 is practiced by etching. To avoid the problems of the traditional methods of etching the spacers described in FIGS. 1b to 1d, it is necessary that the etching of the modified dielectric layer 158 is as selective as possible with respect to the silicon in particular so as not to attack the monocrystalline silicon source / drain areas with the disadvantages and consequences described above.
    According to one embodiment, prior to removal of the modified dielectric layer, a (pre-) annealing 443 under vacuum is carried out at a temperature preferably above 100 ° C to remove all the moisture on the surface of the plate. The waiting time between the pre-annealing 443 and the dry etching 441 based on hydrofluoric acid (HF) gas must be kept to a minimum. By way of preference, the pre-annealing 443 and the dry etching 441 based on hydrofluoric acid HF must be carried out in the same tool.
    The shrinkage 440 of the modified dielectric layer 158 advantageously comprises a dry etching 441, preferably based on hydrofluoric acid (HF) for a dielectric layer 152, for example based on silicon nitride, combined with a removal 442 of residues non-volatile present on the plate containing the devices being manufactured. This simplifies the process and saves time. The thickness of the modified dielectric layer 158 is typically in a range of values from 1 nanometer to a few tens of nanometers. Burning times can range from seconds to minutes. They are obviously directly dependent on the thickness of the dielectric layer that has been modified 158. By way of example, to remove a thickness of 10 nm from the modified dielectric layer 158, it is necessary to form a gaseous mixture whose ratio of the first and second component is thus composed: 31% hydrofluoric acid (HF) gas for 69% nitrogen (N2) sec. An etching time of the order of 2 minutes is required, at ambient temperature and at ambient pressure.
    The dry etching 441 of the modified dielectric layer 158 will also be selective with respect to the silicon oxide. This is particularly the case for making three-dimensional transistors FinFET type. Selective etching with silicon and its oxide (Si / SiO2), accompanied by a removal of surface residues 442, can then also be performed for this step of removing the modified dielectric layer 158.
    This embodiment makes it possible, for example, to obtain a very good selectivity of the etching of the modified nitride relative to the unmodified nitride and to the material of the layer 146 in an unmodified semiconductor material. Advantageously, the selectivities are improved thanks to the gaseous HF, with respect to the liquid HF. In particular, the selectivity is multiplied by 3 on unmodified nitride, by 14 on silicon oxide. On a semiconductor material (for example, Si, SiGe or Ge), the selectivity is infinite.
    It will be noted here that there are etching reactors for performing implantation, for example of hydrogen, from a plasma which can be followed, in the same system, by removing the modified dielectric layer 158 from the plasma. using a dry etching as described above. Thus, it is possible in this case to chain the cycles of modification 430 and withdrawal 440 of the dielectric layer 152 selectively Si or SiO 2, without air release of the plate. This is an additional incentive to use an etching reactor to implement the invention rather than using a standard implanter whenever possible.
    As already mentioned, the modification operations 430 of the dielectric layer 152 and the recess 440 of the modified dielectric layer 158 may optionally be repeated 450 until the dielectric material of the modified dielectric layer 158 disappears on all the horizontal surfaces.
    The following steps of the method are not different from those corresponding to the standard methods where the extensions of the source / drain zones 460 are possibly carried out by ion implantation of dopants before epitaxial growth of the raised source / drain 470 of FDSOI transistors.
    The following table gives typical conditions for implementing step 430 of modifying the dielectric layer 152 in the case of using a standard plasma etching reactor. These conditions are largely dependent on the thickness to be modified in the dielectric layer 152. This is only a particular example of implementation of step 430 for modifying the layer to be etched. As already mentioned, other means can be used for the implantation of light species used to modify the layer to be etched. In particular, it will be possible to use low or high density plasmas or plasmas by immersion. Advantageously, any type of dry etching device is potentially usable and especially those said ICP of English "inductively coupled plasma" that is to say "inductively coupled plasma" or CCP English " capacitively coupled plasma "i.e." capacitively coupled plasma. The possibility of drawing the source and / or the bias also allows to have a better control on the depth of implantation for small thicknesses.
    By way of nonlimiting example of the invention, to modify a thickness of 15 nm of silicon nitride in an ICP type burner (TCP RF), continuously, the ionic energy (or bias voltage) required for a plasma formed from a hydrogen-based component (H), whose flow rate is 50 sccm, for a voltage of 250V for a period of 60 seconds. In this case, the pressure used is 10 mTorr and the power of the source is 500W. The invention is not limited to the only embodiments and embodiments described above, but extends to all embodiments within the scope of the claims.
    The process according to the present invention based on gaseous hydrofluoric acid is carried out at ambient temperature (that is to say between 20 ° C. and 30 ° C.) and at atmospheric pressure 760 Torr. However, controlling the temperature of the HF-based gas so that it is preferentially greater than that of the ambient temperature and / or controlling the pressure so as to be preferentially lower than that of the ambient pressure will lead to to achieve even greater selectivity between a silicon nitride (SiN) layer and a silicon oxide (SiO 2) layer or an unmodified SiN silicon nitride layer by reducing the amount of moisture on the surface of the wafer (in English "wafer").
    权利要求:
    Claims (25)
    [1" id="c-fr-0001]
    A method of forming spacers of a gate (150) of a field effect transistor (100), the gate (150) including flanks and a vertex and being located above a layer (146). ) of a semiconductor material, the method comprising a step (410) of forming a dielectric layer (152) overlying the gate of the transistor, the method comprising: - after the step of forming the dielectric layer (152) at least one step of modifying (430) said dielectric layer (152) by placing the dielectric layer (152) in contact with a plasma creating anisotropic light ion bombardment in a preferred direction parallel to the sides of the gate (120), the plasma conditions, in particular the light ion energy and the implanted dose being chosen so as to modify, by implantation of the light ions, at least portions (158) of the dielectric layer (152) which are located on a peak of the grid and on either side of the grid (120) and which are perpendicular to the sidewalls of the grid (120) while retaining portions of the dielectric layer (152) covering the unmodified sidewalls of the grid (120) or unmodified throughout their thickness; the light ions being ions based on hydrogen (H) and / or based on helium (He); at least one step of removing (440) the modified dielectric layer (158) by selective etching of said modified dielectric layer (158) with respect to the layer (146) in a semi-material -conductor and vis-à-vis the dielectric layer (152) unmodified; characterized in that the step of removing (440) the modified dielectric layer (158) comprises: - a dry etching (441) carried out by placing a gaseous mixture, preferably a gaseous mixture, comprising at least a first component based on hydrofluoric acid (HF), the hydrofluoric acid transforming into non-volatile residues at room temperature the modified dielectric layer (158), - only after the dry etching (441): a withdrawal (442) of non-volatile residues -Volatile at room temperature by wet cleaning or thermal sublimation annealing.
    [2" id="c-fr-0002]
    2. Method according to the preceding claim wherein the parameters of the step of removing (440) the modified dielectric layer (158), in particular the gas ratio between the first component and the second component used in the dry etching, are provided so that the modified dielectric layer (158) can be selectively etched on the layer (146) of a semiconductor material and vis-à-vis the dielectric layer (152). changed.
    [3" id="c-fr-0003]
    3. Method according to the preceding claim wherein the first component is generated by evaporation from a liquid source or from a pressurized bottle.
    [4" id="c-fr-0004]
    4. Method according to any one of the preceding claims wherein said bringing into contact is carried out in a chemical reactor.
    [5" id="c-fr-0005]
    5. Method according to the preceding claim wherein the reactor comprises an enclosure and wherein the bringing into contact is carried out at room temperature and atmospheric pressure or is carried out at a temperature above room temperature and at a pressure below atmospheric pressure.
    [6" id="c-fr-0006]
    6. Method according to any one of the preceding claims wherein the gaseous mixture comprises a second component based on an inert gas selected from nitrogen (N2) and / or argon (Ar).
    [7" id="c-fr-0007]
    7. Method according to the preceding claim wherein the ratio of gas between the first component and the second component is between 1: 25 and 1: 1.
    [8" id="c-fr-0008]
    8. A method according to any one of the preceding claims wherein the dry etching (441) is carried out at a temperature between 15 ° C and 80 ° C, a pressure of between 40 Torr to 760 Torr, for a period ranging from a few seconds to minutes.
    [9" id="c-fr-0009]
    9. A process according to any one of the preceding claims wherein the removal (442) of nonvolatile residues at room temperature comprises sublimation thermal annealing carried out at a temperature between 200 ° C and 400 ° C.
    [10" id="c-fr-0010]
    10. Method according to the preceding claim wherein the annealing is performed under a low pressure of between 10.10'3 Torr and 2 Torr.
    [11" id="c-fr-0011]
    11. Method according to any one of the two preceding claims wherein the annealing is carried out for a time of between 60 and 600 seconds.
    [12" id="c-fr-0012]
    The method of any one of claims 1 to 8 wherein the removal (442) of nonvolatile residues at room temperature comprises a deionized water-based wet cleaning.
    [13" id="c-fr-0013]
    13. A method according to any one of the preceding claims comprising, prior to the step of removing (440) the modified dielectric layer (158), thermal annealing under vacuum, at a temperature above 100 ° C.
    [14" id="c-fr-0014]
    A method according to any one of the preceding claims wherein the dielectric layer (152) is formed of one or more dielectric materials whose dielectric constant k is less than or equal to 7.
    [15" id="c-fr-0015]
    The method of any of the preceding claims wherein the dielectric layer (152) is a nitride layer.
    [16" id="c-fr-0016]
    The method of any of the preceding claims wherein the dielectric layer (152) is a silicon-based (Si) layer.
    [17" id="c-fr-0017]
    17. A method according to any one of the preceding claims wherein the material of the dielectric layer (152) is selected from: SiCO, SiC, SiCN, SiON, SiOCN, SiCBN, SiOCH, SiOx by example the Si02.
    [18" id="c-fr-0018]
    18. A method according to any one of the preceding claims wherein the semiconductor material is silicon and wherein the step of removing (440) the modified dielectric layer (158) is performed in part at least by dry etching ( 441) selectively to silicon (Si) and / or silicon oxide (SiO2) (121, 740).
    [19" id="c-fr-0019]
    19. A method according to any one of the preceding claims comprising a single modification step (430) performed so as to modify the dielectric layer (152) throughout its thickness on all the surfaces parallel to the plane of a substrate on which rests the grid (150) and not to modify the dielectric layer (152) throughout its thickness on the surfaces perpendicular to this plane.
    [20" id="c-fr-0020]
    The method according to any one of the preceding claims, wherein the layer (146) of a semiconductor material is selected from: silicon (Si), germanium (Ge), silicon-germanium (SiGe), and wherein the light ions are taken from helium (He) and / or hydrogen (H2) and / or ammonia (NH3).
    [21" id="c-fr-0021]
    21. Process according to any one of the preceding claims, in which the light ions are based on hydrogen and the flow rate of the light ions based on hydrogen (H) is between 10 and 500 sccm (cubic centimeter per minute). the hydrogen-based ions (H) being taken from: H, H +, H2 +, H3 +.
    [22" id="c-fr-0022]
    22. The process as claimed in claim 1, in which the light ions are based on helium and the flow rate of the light helium (He) ions is between 50 and 500 sccm.
    [23" id="c-fr-0023]
    A method according to any one of the preceding claims wherein the step of modifying (430) the dielectric layer (152) is performed with a bias power or source power of between 20V (volts) and 500V, with a pressure between 5 mTorr (milliTorr) and 100 mTorr, at a temperature between 10 ° C and 100 ° C, for a period of seconds to a few hundred seconds.
    [24" id="c-fr-0024]
    The method of any of the preceding claims wherein the step of modifying (430) the dielectric layer (152) made from a plasma changes the dielectric layer (152) continuously from the surface of the dielectric layer (152) and a thickness between 1 nm (nm) and 30 nm, preferably between 1 nm and 10 nm.
    [25" id="c-fr-0025]
    25. The method as claimed in claim 1, in which the transistor is a FDSOI type or FinFET type transistor.
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    同族专利:
    公开号 | 公开日
    EP3144973B1|2020-03-04|
    FR3041471B1|2018-07-27|
    US20170084720A1|2017-03-23|
    US10043890B2|2018-08-07|
    EP3144973A1|2017-03-22|
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    优先权:
    申请号 | 申请日 | 专利标题
    FR1558845A|FR3041471B1|2015-09-18|2015-09-18|METHOD FOR FORMING SPACERS OF A GRID OF A TRANSISTOR|
    FR1558845|2015-09-18|FR1558845A| FR3041471B1|2015-09-18|2015-09-18|METHOD FOR FORMING SPACERS OF A GRID OF A TRANSISTOR|
    US15/267,624| US10043890B2|2015-09-18|2016-09-16|Method of forming spacers for a gate of a transistor|
    EP16189263.3A| EP3144973B1|2015-09-18|2016-09-16|Method for forming spacers of a transistor gate|
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